A post layout watermarking method for IP protection

We propose a new watermarking system for VLSI layout design intellectual property protection (IPP) that will not damage circuit properties. The previous studies for layout design IPP are mainly restricted to pre-layout design, i.e. they would increase layout size and vary signal timing. The idea of our system is to use a special incremental router that removes wires of target nets and re-routes them by inserting redundant bends. We can distinguish the marked net from others. This redundant insertion is not always possible according to wire density around the wire, thus we use it iteratively. We evaluated the success possibilities of our watermarking system in various wire density benchmark circuits experimentally and found more than three iterations are enough for the practical post layout design to achieve successful watermarking.