Floorplanning with clock tree estimation

Traditional floorplanners determine the module topology for the minimization of total chip area, total wirelength, and routing congestion. However, as design complexity continues to increase, it is necessary to reduce the clock skew and estimate the clock latency during floorplanning. We propose a two-stage simulated annealing (SA) floorplanner based on sequence-pair representation. A clock tree estimation model is embedded into the floorplanner to guide the process of floorplan generation. Our clock tree model includes two parts. First, we use an H-tree algorithm to predict an intra-module clock tree for each module. Second, the DME algorithm is applied for inter-module clock tree generation. Experimental data show that both the clock tree wirelength and the clock latency can be improved simultaneously, while the extra overhead on the chip area is small.