Propagation delay fault: a new fault model to test delay faults

A new fault model, named propagation delay fault model, is proposed to test the gross gate delay defects modeled at each gate terminal and the distributed delay defects in the fault propagation paths. The proposed fault model assumes that the sum of the gross gate delay defect and the distributed delay defect are large enough to cause timing violation for all the paths passing through the fault site and the fault propagation path. Experimental results demonstrate that high fault coverage can be achieved in a reasonable amount of time and the test set size is comparable to the test set size generated for the transition fault model.