Floorplanning for 3-D VLSI design

In this paper, we present a floorplanning algorithm for 3D ICs. The problem can be formulated as that of packing a given set of 3D rectangular blocks while minimizing a suitable cost function. Our algorithm is based on a generalization of the classical 2D slicing floorplans to 3D slicing floorplans. A new encoding scheme of slicing floorplans (2D/3D) and its associated set of moves form the basis of the new simulated annealing based algorithm. The best-known algorithm for packing 3D rectangular blocks is based on simulated annealing using sequence-triple floorplan representation. Experimental results show that our algorithm produces packing results on average 3% better than the sequence-triple-based algorithm under the same annealing parameters, and our algorithm runs much faster (17 times for problems containing 100 blocks) than the sequence-triple. Moreover, our algorithm can be extended to consider various types of placement constraints and thermal distribution while the existing sequence-triple-based algorithm does not have such capabilities. Finally, when specializing to 2D problems, our algorithm is a new 2D slicing floorplanning algorithm. We are excited to report the surprising results that our new 2D floorplanner has produced slicing floorplans for the two largest MCNC benchmarks ami33 and ami49 which have the smallest areas (among all slicing/nonslicing floorplanning algorithms) ever reported in the literature.