1T-1C FRAM cell reading without reference-voltage generation

Reading 2T-2C ferroelectric random-access memory (FRAM) cells does not require generating a reference voltage as this architecture is self-referenced. However, this architecture consumes a relatively large silicon area. So, 1T-1C FRAMs are used instead. Reading 1T-1C FRAMs, however, requires generating a reference voltage that is ideally halfway between the bitline voltage generated in case of “0” reading, V₀, and in case of “1” reading, V₁. Then, this reference voltage will be compared with the bitline voltage by a sense amplifier. In this paper, a preview of some of the schemes that does not require generating a reference voltage will be introduced. Then, a novel reading scheme that does not require the generation of a reference voltage and depends on using two cascaded inverters is discussed. The proposed scheme will be simulated for the 0.13 μm CMOS technology and shows a 60% reduction in the read access time for stored “1”. The reduction in the read access time can be attributed to the fact that the output data will be taken at a parasitic capacitance that is much smaller than the bitline parasitic capacitance.