Single-track asynchronous pipeline controller design

Various applications have demonstrated that asynchronous circuits have great potential for energy-efficient and high-performance design. It is well known that asynchronous pipeline serves as a powerful method of implementing general computation. This paper presents a new fast asynchronous pipeline controller with the forward and reverse latency of 2 transitions and a new robust QDI asynchronous pipeline controller using Muller C-gate. The first controller reduces 38.1% forward latency comparing to the recently proposed ultra-high-speed GasP circuit, the controller can run at 2.2 GHz using TSMC 0.25 um process. The second controller greatly simplifies the timing verifications with lower area cost than STFB circuit.