Title :
Adiabatic CMOS gate and adiabatic circuit design for low-power applications
Author_Institution :
Dept. of Inf. & Electron. Eng., Zhejiang Univ., Hangzhou, China
Abstract :
The methodology for designing adiabatic circuits employing two-phase power clock, is investigated. First, algebraic expressions for and properties of power-clocked signals are discussed. Then the design of adiabatic gates based on AC power supply and CMOS transmission gates is analyzed. On this basis, basic rules for the design of adiabatic circuits are proposed, and a design example of an adiabatic full adder is demonstrated. SPICE simulations using a trapezoidal power-clock demonstrate that the designed adiabatic circuits have a correct logic function and ultra low-power characteristics.
Keywords :
CMOS logic circuits; SPICE; logic design; logic gates; low-power electronics; power supply circuits; AC power supply; CMOS transmission gates; SPICE simulations; adiabatic CMOS gate; adiabatic circuit design; adiabatic full adder; logic function; low power applications; power-clocked signals; two phase power clock; Adders; Circuit simulation; Circuit synthesis; Clocks; Combinational circuits; Design methodology; Logic circuits; Logic functions; SPICE; Signal design;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466466
