Substrate noise modeling in early floorplanning of MS-SOCs

We propose a frequency-dependent sensitivity model for analog blocks and a noise injection model for digital blocks in application to early design planning of mixed-signal system-on-chips (MS-SOCs). We assume no precise layout information about IP cores is available. We also propose an empirical formula for separation-dependent coupling between large-area noisy ports and small-area sensitive ports for lightly-doped substrates that are preferred for mixed-signal circuits. The interaction between digital and analog blocks is incorporated into our floorplanner, which reduces the overall noise and the number of analog blocks with noise limit violations. Experimental results on examples created from MCNC floorplanning benchmarks are very encouraging.