Optimal module and voltage assignment for low-power

Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study functional unit binding (or module assignment) given a scheduled data flow graph under a dual-V_dd framework. We assume that each functional unit can be driven by a low V_dd or a high V_dd dynamically during run time to save dynamic power. We develop a polynomial-time optimal algorithm for assigning low V_dd to as many operations as possible under the resource and time constraint, and in the same time minimizing total switching activity through functional unit binding. Our algorithm shows consistent improvement over a design flow that separates voltage assignment from functional unit binding. We also change the initial scheduling to examine power-latency tradeoff scenarios. Experimental results show that we can achieve a 21% power reduction when latency bound is tight. When latency is relaxed by 10 to 100%, the power reduction is 31 to 73% compared to the synthesis results for the case of single high V_dd without latency relaxation. We also show comparison data of energy consumption under the same experimental setting.