Title :
Design of a high performance FFT processor based on FPGA
Author :
Chu Chad ; Qin, Zhang ; Yingke, Xie ; Chengde, Han
Author_Institution :
Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China
Abstract :
The design method of a real-time FFT processor is presented. By optimizing algorithm of memory mapping and generation of twiddle factors, a radix-4 butterfly can be calculated in one clock cycle. An approach to adaptive overflow control is also introduced to avoid overflow without interrupting the computing pipeline. The design is implemented on a FPGA chip and achieves the operating frequency at 127 MHz. It can complete a complex 1024-point FFT within 10.1 μs.
Keywords :
digital signal processing chips; fast Fourier transforms; field programmable gate arrays; pipeline arithmetic; 127 MHz; FPGA chip; address generation; computing pipeline; memory mapping; overflow control; real-time FFT processor; twiddle factors; Chaos; Clocks; Digital signal processing; Discrete Fourier transforms; Field programmable gate arrays; Frequency; Hardware; High performance computing; Programmable logic arrays; Signal processing algorithms;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466489
