REMIC - design of a reactive embedded microprocessor core

Author

Salcic, Zoran ; Hui, Dong ; Roop, Panho ; Biglari-Abhari, Morteza

Author_Institution

Dept. of Electr. & Comput. Eng., Auckland Univ., New Zealand

Volume

2

fYear

2005

fDate

18-21 Jan. 2005

Firstpage

977

Abstract

Reactivity on external events is an important feature of almost all embedded systems. In this paper we present the design of a new, reactive embedded microprocessor called REMIC, that supports reactivity in a new way following the paradigm of synchronous system level language Esterel. The rationale for REMIC design, its novel features with the design details and some performance figures are presented to demonstrate its suitability for embedded systems. Besides single processor systems, REMIC can be easily combined into multiple processor architectures that support real concurrency.

Keywords

embedded systems; microcomputers; microprocessor chips; Esterel; REMIC design; concurrency; embedded systems; external events reactivity; multiple processor architectures; reactive embedded microprocessor core; single processor systems; synchronous system level language; Computer languages; Concurrent computing; Control systems; Embedded system; Instruction sets; Microprocessors; Operating systems; Process design; Real time systems; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific

Print_ISBN

0-7803-8736-8

Type

conf

DOI

10.1109/ASPDAC.2005.1466503

Filename

1466503