Power minimization for dynamic PLAs

Author

Tien, Tzyy-Kuen ; Tsai, Chih-Shen ; Chang, Shih-Chieh ; Yeh, Chingwei

Author_Institution

Southern Taiwan Univ. of Technol., China

Volume

2

fYear

2005

fDate

18-21 Jan. 2005

Firstpage

1010

Abstract

In this paper, we propose a new dynamic PLA structure which incorporates super product lines. A super product line adds the NAND functionality on top of the NOR structure, thus lowering the switching activities in the product lines as well as power consumption. Since there are many candidates for super product lines, we have developed a CAD algorithm based on the maximum weighted matching to find optimal solution. The post simulation results show significant reduction in power consumption. On the average, the power consumption can be saved 58.9% and the delay overhead is merely 1.6% for 18 circuits.

Keywords

power consumption; power supply circuits; programmable logic arrays; CAD algorithm; NAND functionality; NOR structure; delay overhead; dynamic PLA structure; maximum weighted matching; optimal solution; power consumption; power minimization; programmable logic arrays; switching activity; Boolean functions; Capacitance; Circuit simulation; Contracts; Delay; Energy consumption; Equations; Merging; Minimization; Programmable logic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific

Print_ISBN

0-7803-8736-8

Type

conf

DOI

10.1109/ASPDAC.2005.1466511

Filename

1466511