Title :
Integrated algorithmic logical and physical design of integer multiplier
Author :
Zhou, Shuo ; Yao, Bo ; Liu, Jian-Hua ; Cheng, Chung-Kuan
Author_Institution :
Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
Abstract :
This paper presents an integrated methodology for high-performance integer multiplier design, which combines algorithmic partial product generation, logic synthesis, and physical layout into a unified process. The interconnect delay, which dominates the performance of a multiplier, is thoroughly considered in this integration. The special structures in the multiplier are utilized to reduce the high complexity of the holistic approach. Compared with multipliers generated by a state-of-the-art tool, the timing improvements of our results are 11% for a 16-bit multiplier, and 7.5% for a 32-bit multiplier.
Keywords :
interconnections; logic circuits; logic design; multiplying circuits; 16-bit multiplier; 32-bit multiplier; algorithmic partial product generation; holistic approach; integer multiplier; integrated algorithmic logical design; integrated algorithmic physical design; integrated methodology; interconnect delay; logic synthesis; partial Product; state-of-the-art tool; Algorithm design and analysis; Delay estimation; Encoding; Integrated circuit interconnections; Integrated circuit synthesis; Logic; Optimization methods; Process design; Timing; Wire;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466512
