Integrated algorithmic logical and physical design of integer multiplier

This paper presents an integrated methodology for high-performance integer multiplier design, which combines algorithmic partial product generation, logic synthesis, and physical layout into a unified process. The interconnect delay, which dominates the performance of a multiplier, is thoroughly considered in this integration. The special structures in the multiplier are utilized to reduce the high complexity of the holistic approach. Compared with multipliers generated by a state-of-the-art tool, the timing improvements of our results are 11% for a 16-bit multiplier, and 7.5% for a 32-bit multiplier.