Title :
Forward symbolic model checking for real time systems
Author :
Logothetis, Georgios
Author_Institution :
Dept. of Comput. Sci., Karlsruhe Univ., Germany
Abstract :
Synchronous languages are widely used in industrial applications for the design and implementation of real-time embedded and reactive systems and are also well-suited for real-time verification purposes, since they have clean formal semantics. In this paper we focus on the real-time temporal logic JCTL, which can directly support the real-time formal verification of synchronous programs for the design of systems in earlier (high-level) as well as in later (low-level) design stages, creating a bridging between industrial real-time descriptions and formal real-time verification. We extend the model-checking capabilities of JCTL, by introducing new forward symbolic model-checking techniques, allowing JCTL to benefit from both, forward-, as well as traditional backward state traversal methods and of course, their combination.
Keywords :
embedded systems; formal verification; logic design; temporal logic; JCTL; backward state traversal methods; formal real-time verification; formal semantics; formal verification; forward symbolic model checking; reactive systems; real time systems; real-time descriptions; synchronous languages; synchronous programs; temporal logic; Computer science; Error correction; Fault tolerance; Formal verification; Hardware design languages; Logic design; Real time systems; Runtime; Synchronous generators;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466519