Title :
Fast floorplanning by look-ahead enabled recursive bipartitioning
Author :
Cong, Jason ; Romesis, Michail ; Shinned, J.R.
Author_Institution :
Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
Abstract :
A new paradigm is introduced for floorplanning any combination of fixed-shape and variable-shape blocks under tight fixed-outline area constraints and a wirelength objective. Dramatic improvement over traditional floor-planning methods is achieved by explicit construction of strictly legal layouts for every partition block at every level of a cutsize-driven, top-down hierarchy. By scalably incorporating legalization into the hierarchical flow, post-hoc legalization is successfully eliminated. For large floorplanning benchmarks, an implementation, called PATOMA, generates solutions with half the wirelength of state-of-the-art floorplanners in orders of magnitude less run time.
Keywords :
VLSI; integrated circuit layout; logic partitioning; PATOMA; area constraints; cutsize-driven hierarchy; fast floorplanning; fixed-shape blocks; look-ahead enabled recursive bipartitioning; strictly legal layouts; top-down hierarchy; variable-shape blocks; wirelength objective; Art; Circuits; Clustering algorithms; Computer science; Law; Legal factors; Logic design; Simulated annealing; Traffic control; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466537