Title :
An LP-based methodology for improved timing-driven placement
Author :
Wang, Qingzhou ; Lillis, John ; Sanyal, Shubhankar
Author_Institution :
Dept. of Comput. Sci., Univ. of Illinois at Chicago, IL, USA
Abstract :
A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formulation captures all topological paths in a linear sized LP and thus, heuristic net weights or net budgets are not necessary. Additionally, explicit enumeration of a large number of paths is avoided. The flow begins with a given placement and iteratively extracts timing-critical sub-circuits, optimally places the sub-circuit by LP and applies a timing-driven legalizer. The approach is applied to the FPGA domain and yields an average of 19.6% reduction in clock period of routed MCNC designs versus I.6J (with reductions up to 39.5%).
Keywords :
field programmable gate arrays; integrated circuit layout; iterative methods; linear programming; FPGA; LP-based methodology; MCNC designs; improved timing-driven placement; linear programming; relaxed placement; timing-driven legalizer; Clocks; Computer science; Delay; Field programmable gate arrays; Integrated circuit interconnections; Linear programming; Routing; Scalability; Simulated annealing; Timing;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466542