Title :
Register-transfer level functional scan for hierarchical designs
Author :
Ko, Ho Fai ; Xu, Qiang ; Nicolici, Nicola
Author_Institution :
Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada
Abstract :
This paper discusses the potential benefits of inserting scan chains (SCs) in hierarchical designs at the register-transfer level (RTL) of design abstraction. Using new algorithms for functional scan chain design, it is shown how tight timing constraints for design-for-test (DFT) planning at RTL can improve the performance of a circuit, when compared to its gate level counterpart, without any loss in testability.
Keywords :
boundary scan testing; design for testability; digital integrated circuits; integrated circuit design; integrated circuit testing; logic design; logic testing; design abstraction; design-for-test planning; functional scan; gate level; hierarchical designs; register-transfer level; scan chains; timing constraints; Circuit synthesis; Circuit testing; Constraint optimization; Costs; Flexible printed circuits; Greedy algorithms; Logic circuits; Logic testing; Routing; Timing;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466550
