Title :
A retention-aware test power model for embedded SRAM
Author :
Wang, Baosheng ; Yang, Josh ; Wu, Yuejian ; Ivanov, André
Author_Institution :
Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada
Abstract :
This paper addresses the test power model problem for embedded SRAMs (e-SRAMs). Previous researches treat e-SRAMs the same as other SoC core and use a "single-rectangle" power model to describe their test power consumption. This leads to significant waste of test time since e-SRAM test usually includes a long period of "zero" power consumption for the detection of data retention faults, This paper takes advantage of this "zero" power period and proposes a "retention-aware" test power model for e-SRAMs. The proposed model is evaluated and its impact on test time reduction is reported for various scenarios in terms of retention test duration, memory capacities, test algorithm complexities, etc. A formula is derived to predict the maximum test time reduction when the "zero" power period is fully utilized in a SoC environment.
Keywords :
SRAM chips; embedded systems; integrated circuit modelling; integrated circuit testing; logic testing; optimisation; scheduling; system-on-chip; SoC core; data retention fault test; data retention faults; e-SRAM; embedded SRAM; memory capacities; retention test duration; test algorithm complexities; test power consumption; test power model; test scheduling; test time reduction; Delay; Energy consumption; Fault detection; Logic testing; Power engineering and energy; Power engineering computing; Random access memory; Semiconductor device testing; System testing; System-on-a-chip;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466552
