Title :
On-chip accumulated jitter measurement for phase-locked loops
Author :
Li, Chih-Feng ; Yang, Shao-Sheng ; Chang, Tsin-Yuan
Author_Institution :
Dept. of Electr. Eng., National Tsing-Hua Univ., Hsinchu, Taiwan
Abstract :
A time-to-digital converter (TDC) circuit is presented to measure the worst-case accumulated jitters over N periods of clock produced by the PLL. Including the most positive jitter and the most negative jitter, the worst case jitters can be calculated through the proposed approach. In a case-study, by applying the proposed TDC circuit with 4-bit flash ADC and the accumulated period N=8, the frequency range of the measured signal, resolution and linearity error are 0.7-1.4GHZ, 44ps and 1.25%, respectively. Using a 0.25um 1P6IM CMOS process, the HSPICE simulation result shows that the maximum measurement error is 1 LSB after calibration.
Keywords :
CMOS integrated circuits; SPICE; analogue-digital conversion; circuit simulation; clocks; phase locked loops; system-on-chip; timing jitter; 0.25 micron; 0.7 to 1.4 GHz; CMOS process; HSPICE simulation; clock; flash ADC; jitter measurement; phase-locked loops; time-to-digital converter circuit; CMOS process; Circuit simulation; Clocks; Frequency measurement; Jitter; Linearity; Measurement errors; Phase locked loops; Phase measurement; Signal resolution;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466553
