Static power minimization in current-mode circuits

Author

Bhat, M.S. ; Jamadagni, H.S.

Author_Institution

Centre for Electron. Design & Technol., Indian Inst. of Sci., Bangalore, India

Volume

2

fYear

2005

fDate

18-21 Jan. 2005

Firstpage

1220

Abstract

We propose a method involving selective signal gating to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present an approximation model for current in a current comparator circuit Power reduction is achieved by turning off the redundant comparator circuits using a switch-architecture. Simulations are carried-out for current-mode flash ADC designs and literal generating circuits for MVL to validate the method.

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; current comparators; current-mode circuits; multivalued logic circuits; current approximation model; current comparators; current-mode CMOS analog; current-mode circuits; current-mode flash ADC designs; multiple-valued logic circuits; power dissipation; power reduction; redundant comparator circuits; static power minimization; switch architecture; CMOS logic circuits; CMOS technology; Communication switching; Current mode circuits; Logic circuits; Minimization; Power dissipation; Signal design; Signal generators; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific

Print_ISBN

0-7803-8736-8

Type

conf

DOI

10.1109/ASPDAC.2005.1466562

Filename

1466562