Title :
A novel transmitter for 1000 base-T physical transceiver
Abstract :
This paper describes a transmitter used in 1000 base-T PHY chip. A digital-to-analog converter with 5bit resolution, 8bit accuracy, 125MHz sample rate and 4ns transition timing has been implemented to satisfy all the specifications of the gigabit Ethernet transmitter defined in IEEE 802.3 standard. The entire design occupies 0.4 X 0.6mm2 in a 0.18-μum CMOS technology. And the design ensures no other power dissipation inside the transmitter except the digital decoder block. Most power will distribute to the peripheral interface circuit with the twisted-pair used in the transmitter front-end.
Keywords :
IEEE standards; integrated circuit design; local area networks; peripheral interfaces; transceivers; 0.18 micron; 0.4 mm; 0.6 mm; 1000 base-T PHY chip; 125 MHz; 4 ns; CMOS technology; IEEE 802.3 standard; digital decoder block; digital-to-analog converter; gigabit Ethernet transmitter; peripheral interface circuit; physical transceiver; power dissipation; transmitter front-end; CMOS technology; Circuits; Decoding; Digital-analog conversion; Ethernet networks; Physical layer; Power dissipation; Timing; Transceivers; Transmitters;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466563
