Using GALS architecture to reduce the impact of long wire delay on FPGA performance

Interconnect delay is becoming a major roadblock to FPGA performance with technology scaling and growing chip sizes. globally asynchronous locally synchronous (GALS) design is considered a potential solution to this issue. An important design decision in building a GALS FPGA architecture is to determine the appropriate GALS island size. A large GALS island will reduce the asynchronous communication overhead but the interconnect delay inside an island is increased. On the other hand, asynchronous communication overhead could be a major concern for a small GALS island size. In this paper, we propose a design flow to investigate this tradeoff. The input circuit is first divided into partitions according to the specified GALS island size and each partition is then implemented with commercially available CAD tools. The overall system performance is estimated by a performance evaluator. Experimental results validate our design flow and show a performance improvement of around 20% by adopting a GALS architecture.