Reducing leakage power in instruction cache using WDC for embedded processors

Power consumption is an important design issue of current embedded systems and SoC. It has been shown that instruction cache accounts for a significant portion of the power dissipation of the whole processor chip. WDC (way-decay cache) proposed in this paper is a novel cache architecture with resizable associativity and low leakage power. Experiment results show that for the SPECint95 benchmarks, WDC reduces energy consumption without significantly hindering performance.