A novel O(n) parallel banker´s algorithm for system-on-a-chip

This paper proposes a novel O(n) parallel banker´s algorithm (PBA) with a best-case run-time of O(1), reduced from an O(mn²) run-time complexity of the original banker´s algorithm. We implemented the approach in hardware, which we call PBA unit (PBAU), using Verilog HDL and verified the runtime complexity. PBAU is an intellectual property (IP) block that provides a mechanism of very fast, automatic deadlock avoidance for a multiprocessor system-on-a-chip (MPSoC, which we predict will be the mainstream of future high performance computing environments). Moreover, our PBA supports multiple-instance multiple resource systems. We demonstrate that PBAU not only avoids deadlock in a few clock cycles (1600× faster than the banker´s algorithm in software) but also achieves in a particular example a 19% speedup of application execution time over avoiding deadlock in software. Lastly, the MPSoC area overhead due to PBAU is small, under 0.05% in our candidate MPSoC example.