DocumentCode
3548441
Title
Design and measurement of 6.4 Gbps 8:1 multiplexer in 0.18μm CMOS process
Author
Shinmyo, A. ; Hashimoto, Masanori ; Onodera, Hidetoshi
Author_Institution
Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
Volume
2
fYear
2005
fDate
18-21 Jan. 2005
Abstract
We develop and measure a 8:1 multiplexer in a CMOS 0.18μm process. We design the hybrid multiplexer based on a prior detailed performance evaluation both of CMOS static and current mode logic circuits, and build a hybrid structure. The fabricated chip operates at up to 6.4 Gbps with power consumption of 84mW.
Keywords
CMOS logic circuits; circuit CAD; current-mode circuits; high-speed integrated circuits; integrated circuit design; integrated circuit measurement; logic CAD; multiplexing equipment; 0.18 micron; 6.4 Gbit/s; 84 mW; 8:1 multiplexer; CMOS current mode logic circuits; CMOS process; CMOS static logic circuits; hybrid multiplexer; Area measurement; CMOS logic circuits; CMOS process; Energy consumption; Frequency conversion; Frequency measurement; Logic design; Multiplexing; Process design; Semiconductor device measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN
0-7803-8736-8
Type
conf
DOI
10.1109/ASPDAC.2005.1466602
Filename
1466602
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