Pattern sensitive fault testing of RAMs with built-in ECC

The problem of testing RAMs with different built-in error-correction-coding (ECC) capabilities is formulated. The basics of ECC in RAMs are reviewed, and some of the implementation aspects are described. It is shown that if memories using separable linear codes satisfy certain conditions, it is always possible to apply arbitrary patterns to all check bits. An upper bound on the number of writes required to apply the required patterns to a neighborhood is established. An efficient algorithm for testing the information bits and check bits of an N-bit memory array for 5 cell neighborhood pattern sensitive faults in O(N) reads and writes is provided. The use of the method is demonstrated by a case study.<>