Parallel prefix adder design with matrix representation

Author

Choi, Youngmoon ; Swartzlander, Earl E., Jr.

Author_Institution

Sun MicroSystems Inc., Austin, TX, USA

fYear

2005

fDate

27-29 June 2005

Firstpage

90

Lastpage

98

Abstract

The paper presents a one-shot batch process that generates a wide range of designs for a group of parallel prefix adders. The prefix adders are represented by two two-dimensional matrices and two vectors. This matrix representation makes it possible to compose two functions for gate sizing which calculate the delay and the total transistor width of the carry propagation graph of adders. After gate sizing, the critical path net-lists of the carry propagation graph are generated from the matrix representation for spice delay calculation. The process is illustrated by generating sets of delay and total transistor width pairs for 32-bit and 64-bit cases.

Keywords

SPICE; adders; carry logic; graph theory; logic design; logic gates; matrix algebra; summing circuits; carry propagation graph; critical path net-lists; one-shot batch process; parallel prefix adder design; spice delay calculation; two-dimensional matrices; Character generation; Concurrent computing; Design engineering; Difference equations; Digital arithmetic; Performance analysis; Propagation delay; Signal generators; Sun;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Arithmetic, 2005. ARITH-17 2005. 17th IEEE Symposium on

ISSN

1063-6889

Print_ISBN

0-7695-2366-8

Type

conf

DOI

10.1109/ARITH.2005.35

Filename

1467627