• DocumentCode
    3549692
  • Title

    Yield challenges in nanotechnology

  • Author

    Ang, K.C.

  • Author_Institution
    Chartered Semicond. Manuf. Ltd, Singapore, Singapore
  • fYear
    2005
  • fDate
    27 June-1 July 2005
  • Firstpage
    1
  • Abstract
    Summary form only given. As semiconductors enter into the era of nanotechnology, fast yield ramp becomes a critical success factor for 300-mm manufacturing, enabling quick product time to market. Hence, the implementation of enhanced yield improvement techniques is essential to meet the yield challenge. This presentation covers the state-of-the-art automation, advanced integrated yield systems, in-line process control, metrology and inspection/electrical testing and enhanced physical and failure analysis techniques for Chartered Fab 7, 300-mm nanotechnology Fab. It also demonstrates the combination of intelligent automation and advanced integrated yield system capability for providing real time, fast and accurate feedback to drive yield improvement and yield prediction.
  • Keywords
    failure analysis; integrated circuit testing; integrated circuit yield; nanotechnology; process control; time to market; advanced integrated yield systems; enhanced yield improvement; failure analysis; in-line process control; inspection/electrical testing; integrated circuit metrology; intelligent automation; nanotechnology; state-of-the-art automation; time to market; yield prediction; Automatic testing; Failure analysis; Inspection; Manufacturing automation; Metrology; Nanotechnology; Process control; Semiconductor device manufacture; System testing; Time to market;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the
  • Print_ISBN
    0-7803-9301-5
  • Type

    conf

  • DOI
    10.1109/IPFA.2005.1469118
  • Filename
    1469118