How effective are failure analysis methods for the 65nm CMOS technology node?

Author

Lamy, M. ; Lorut, F. ; de la Bardonnie, M. ; Ross, R. ; Ly, K. ; Wyon, C. ; Kwakman, L.F.Tz.

Author_Institution

STMicroelectron., Crolles, France

fYear

2005

fDate

27 June-1 July 2005

Firstpage

32

Lastpage

37

Abstract

Various 65 nm CMOS technology FA case studies have been presented and it is concluded that to maintain a high FA success rate for <65nm technologies it is necessary to: (1) improve the characteristics of existing tools considerably: immersion lenses and lock-in amplifiers to improve spatial resolution and detection sensitivity of laser stimulation methods were tested. For SEM imaging, newest generation, high resolution columns exhibiting significantly better performances at low electron beam energies (< 1kV) are now in use; and (2) develop new fault isolation methods (Seebeck imaging, Electro-plating localization, RCI) to also cover the most difficult failure analyses of e.g. high resistive structures.

Keywords

CMOS integrated circuits; failure analysis; integrated circuit testing; nanotechnology; scanning electron microscopy; 65 nm; CMOS technology; SEM imaging; failure analysis; fault isolation methods; high resolution columns; immersion lenses; laser stimulation methods; lock-in amplifiers; CMOS process; CMOS technology; Dielectric materials; Failure analysis; Image analysis; Isolation technology; Logic testing; Optimized production technology; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the

Print_ISBN

0-7803-9301-5

Type

conf

DOI

10.1109/IPFA.2005.1469126

Filename

1469126