Successful fault isolation of bit line leakage and leakage suppression by ILD optimization in embedded flash memory

This paper discussed specifically by focusing on failure analysis study for the successful fault isolation of bit line to bit line (BL) leakage and the formation mechanism of electrical conducting path inside inter level dielectric (ILD) oxide between bit lines in flash cell arrays that has extra topography resulting from two stacked poly-Si layers, which causes the abnormal leakage current during the initial cycling test (a few times of erasing and programming) for flash memory device using high voltage application. In addition, we demonstrate the suppression of this leakage current by optimizing ILD deposition process, resulting in the significant yield improvement as well as better process margin across a wafer.