Backside deprocessing technique & its novel fault isolation application

As process technologies are employed below 100nm, microprocessor fault isolation has become even more challenging. In this paper, we present a backside deprocessing methodology which extends fault isolation capability for silicon-on-insulator (SOI) based product. Die level failure analysis case studies using this novel methodology are demonstrated which greatly increase the fail site isolation/defect detection sensitivity with minimum failure analysis turn around time.