DocumentCode :
3549723
Title :
Soft secondary electron programming for floating gate NOR flash EEPROMs
Author :
Kumar, P. Bharath ; Nair, Deleep R. ; Mahapatra, S.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India
fYear :
2005
fDate :
27 June-1 July 2005
Firstpage :
146
Lastpage :
149
Abstract :
A novel scheme called soft secondary electron programming (SSEP) is introduced and shown to be a promising programming mechanism for scaled NOR flash EEPROMs. SSEP involves use of an "optimum" VB that results in a lower drain disturb compared to both channel hot electron (CHE) and channel initiated secondary electron (CHISEL) mechanisms. The concept behind minimizing drain disturb is discussed. SSEP is shown to give faster programming and lower disturb than CHE at all operating conditions, and better program/disturb margin compared to CHISEL at similar program speed or disturb time.
Keywords :
flash memories; hot carriers; logic gates; CHISEL mechanism; NOR flash EEPROM; channel hot electron; channel initiated secondary electron; drain disturb; floating gate EEPROM; soft secondary electron programming; Channel hot electron injection; Character generation; Charge carrier processes; Dielectric measurements; EPROM; Energy consumption; Isolation technology; Performance evaluation; Thickness measurement; Time measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the
Print_ISBN :
0-7803-9301-5
Type :
conf
DOI :
10.1109/IPFA.2005.1469149
Filename :
1469149
Link To Document :
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