Title :
A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology
Author :
Chen, Shih-Hung ; Ker, Ming-Dou ; Chuang, Che-Hao
Author_Institution :
Dept. of ESD & Product Eng., Ind. Technol. Res. Inst., Taiwan
fDate :
27 June-1 July 2005
Abstract :
A new ESD failure mechanism has been found in the analog pins with pure-diode protection scheme during ND-mode ESD stress. The failure is caused by the parasitic npn interaction between ESD protection diode and guard ring structure. The parasitic npn bipolar, which was constructed between the N+/PW diode and the N+/NW guard ring, provides the discharging path between the I/O pad to the grounded VDD under the ND-mode ESD stress to cause a low ESD robustness of the analog I/O cell. The solution to overcome this ESD failure is also proposed.
Keywords :
CMOS analogue integrated circuits; electrostatic discharge; failure analysis; fault diagnosis; integrated circuit reliability; protection; ESD failure mechanism; ESD stress; ND mode; analog I/O cell; analog pins; deep-submicron CMOS technology; discharging path; pure-diode protection scheme; CMOS technology; Circuits; Clamps; Diodes; Electrostatic discharge; Failure analysis; Pins; Protection; Stress; Variable structure systems;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the
Print_ISBN :
0-7803-9301-5
DOI :
10.1109/IPFA.2005.1469163
