Title :
Characterization of various etching techniques for gate level failure analysis and substrate decoration for advanced Cu/low k technologies
Author :
Wu, Huixian ; Cargo, James ; White, Marvin
Author_Institution :
Agere Syst., Allentown, PA, USA
fDate :
27 June-1 July 2005
Abstract :
In this paper, VLSI technology scaling trends and challenges will be addressed. Failure analysis (FA) challenges, and failure modes for advanced technologies will also be presented. Both Cu/low k integration and gate dielectric integration issues will be discussed, followed by characterization of various poly-silicon etches used for gate oxide decoration. Finally, several different silicon substrate decoration techniques will be presented.
Keywords :
VLSI; copper; dielectric materials; etching; failure analysis; fault diagnosis; integrated circuit reliability; integrated circuit technology; silicon compounds; Cu; Cu integration; VLSI technology; etching techniques; failure modes; gate dielectric integration issues; gate level failure analysis; low k integration; low k technologies; poly-silicon etches; silicon substrate decoration techniques; Copper; Delay effects; Dielectric materials; Dielectric substrates; Electromigration; Etching; Failure analysis; Integrated circuit interconnections; Integrated circuit technology; Silicon;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the
Print_ISBN :
0-7803-9301-5
DOI :
10.1109/IPFA.2005.1469171
