DocumentCode
3549767
Title
Novel 20nm hybrid SOI/bulk CMOS technology with 0.183μm2 6T-SRAM cell by immersion lithography
Author
Hou-Yu Chen ; Chang-Yun Chang ; Chien-Chao Huang ; Tang-Xuan Chung ; Sheng-Da Liu ; Jiunn-Ren HwangYi-Hsuan Liu ; Yu-Jun Chou ; Hong-Jang Wu ; King-Chang Shu ; Chung-Kan Huang ; Jan-Wen You ; Jaw-Jung Shin ; Chun-Kuang Chen ; Chia-Hui Lin ; Ju-Wang Hsu ;
Author_Institution
Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan
fYear
2005
fDate
14-16 June 2005
Firstpage
16
Lastpage
17
Abstract
For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate delay (CV/I) at low gate leakage of 20-40A/cm2 have been achieved over previous leading-edge 45nm node version, while maintaining the same sub-threshold leakage (100nA/μm). 10 times reduction of the leakage can be further modulated by a virtual back-gate control. Fine patterning with line pitch of 90nm by immersion lithography is demonstrated, which features 0.183μm2 6T-SRAM cell for 32nm node on-trend scaling.
Keywords
CMOS integrated circuits; SRAM chips; field effect transistors; nanolithography; nanopatterning; silicon-on-insulator; system-on-chip; 1.3 nm; 20 nm; 32 nm; 45 nm; 6T-SRAM cell; 90 nm; CV-I; N-FET; P-FET; SOC application; SiON; fine patterning; gate dielectric; hybrid SOI-bulk CMOS technology; immersion lithography; intrinsic gate delay; leakage reduction; on-trend scaling; sub-threshold leakage; virtual back-gate control; Analog circuits; CMOS technology; Dielectrics; Fabrication; Gate leakage; Lithography; Low-frequency noise; Silicon on insulator technology; Substrates; Thickness control;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN
4-900784-00-1
Type
conf
DOI
10.1109/.2005.1469194
Filename
1469194
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