Author :
Jeamsaksiri, W. ; Linten, D. ; Thijs, S. ; Carchon, G. ; Ramos, J. ; Mercha, A. ; Sun, X. ; Soussan, P. ; Dehan, M. ; Chiarella, T. ; Venegas, R. ; Subramanian, V. ; Scholten, A. ; Wambacq, P. ; Velghe, R. ; Mannaert, G. ; Heylen, N. ; Verbeeck, R. ; Boul
Abstract :
A 90nm CMOS technology has been used as the baseline for a low-cost RF-CMOS platform, with improved analog/RF performances of the active and passive devices. The 65 nm gate length NMOS exhibits 240GHz peak fmax and 170GHz peak f T. A peak Q of 40@5GHz is measured for a symmetrical 2.7 nH above-IC inductor. This combination leads to a world record performance of a monolithic 5 GHz RF CMOS low noise amplifier presenting a very high gain of 18dB and very low noise figure of 1.5dB, for only 4.8mW power consumption.
Keywords :
CMOS integrated circuits; nanotechnology; radiofrequency amplifiers; radiofrequency integrated circuits; 1.5 dB; 170 GHz; 18 dB; 240 GHz; 4.8 mW; 65 nm; 90 nm; 90nm CMOS technology; IC inductor; NMOS; RF CMOS low noise amplifier; RF circuit; active device; analog-RF performance; gate length; low-cost RF-CMOS platform; monolithic amplifier; noise figure; passive device; peak Q factor; CMOS technology; Circuit optimization; High power amplifiers; Inductors; Low-noise amplifiers; MOS devices; Noise figure; Q measurement; Radio frequency; Radiofrequency amplifiers;
