Author :
Nagel, N. ; Olligs, D. ; Polei, V. ; Parascandola, S. ; Boubekeur, H. ; Bach, L. ; Müller, T. ; Strassburg, M. ; Riedel, S. ; Kratzert, P. ; Caspary, D. ; Deppe, J. ; Wilier, J. ; Schulze, N. ; Mikolajick, T. ; Küsters, K.H. ; Shappir, A. ; Redmard, E. ;
Abstract :
A 90nm Twin Flash memory cell with a size of 0.029μm2/bit (3.5F2) is presented. This cell is introduced first in a 1.8V, 2Gbit data flash. The Twin Flash technology is based on a shallow trench isolation (STI) bounded cell with local interconnect (LI) and serves for both advanced code and data flash storage memories. Beyond the 90nm node the scalability of the Twin Flash device is shown for 70 and 60nm node. The 90nm technology and its scaling follow the DRAM scaling path.
Keywords :
DRAM chips; flash memories; integrated circuit interconnections; isolation technology; nanotechnology; 1.8 V; 2 Gbit; 60 nm; 70 nm; 90 nm; DRAM; STI bounded twin flash cell; Twin Flash device; Twin Flash memory cell; Twin Flash technology; data flash storage memory; local interconnect; shallow trench isolation bounded cell; Charge carrier processes; Electron traps; Flash memory cells; Hot carriers; Isolation technology; Random access memory; Scalability; Silicon compounds; Space technology; Transistors;
