Title :
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
Author :
Leobandung, E. ; Nayakama, H. ; Mocuta, D. ; Miyamoto, K. ; Angyal, M. ; Meer, H.V. ; McStay, K. ; Ahsan, I. ; Allen, S. ; Azuma, A. ; Belyansky, M. ; Bentum, R.-V. ; Cheng, J. ; Chidambarrao, D. ; Dirahoui, B. ; Fukasawa, M. ; Gerhardt, M. ; Gribelyuk, M
Author_Institution :
IBM Syst. & Technol. Group, IBM Semicond. R&D Center, Hopewell Junction, NY, USA
Abstract :
A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65μm2 SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.
Keywords :
CMOS integrated circuits; SRAM chips; cache storage; silicon-on-insulator; 76Mb SRAM cache; SOI technology; SOT CMOS technology; bit-line wiring; dual stress liner; dual stress nitride liners; functional dual-core microprocessor test chip; gate oxide; key execution units; low capacitance SRAM cell; CMOS technology; Capacitance; Compressive stress; DSL; Electronic components; Random access memory; Research and development; Silicides; Tensile stress; Wiring;
Conference_Titel :
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-00-1
DOI :
10.1109/.2005.1469238
