Issues and optimization of millisecond anneal process for 45 nm node and beyond

Author

Adachi, K. ; Ohuchi, K. ; Aoki, N. ; Tsujii, H. ; Ito, T. ; Itokawa, H. ; Matsuo, K. ; Suguro, K. ; Honguh, Y. ; Tamaoki, N. ; Ishimaru, K. ; Ishiuchi, H.

Author_Institution

SoC Res. & Dev. Center, Toshiba Corp. Semicond. Co., Kanagawa, Japan

fYear

2005

fDate

14-16 June 2005

Firstpage

142

Lastpage

143

Abstract

We have investigated millisecond anneal, such as laser spike annealing (LSA) and flash lamp annealing (FLA), which substitute for spike RTA as a dopant activation technology of source/drain extension for 45 nm node. Three key issues of gate leakage current, junction leakage current and pattern dependence were discussed from the integration and CMOSFETs performance viewpoint. We reported that LSA is the leading candidate for 45 nm node and beyond.

Keywords

MOSFET; circuit optimisation; laser beam annealing; leakage currents; rapid thermal annealing; semiconductor doping; 45 nm; 45 nm node; CMOSFETs; dopant activation technology; flash lamp annealing; gate leakage current; junction leakage current; laser spike annealing; millisecond anneal process; optimization; pattern dependence; source/drain extension; spike RTA; Annealing; CMOS technology; CMOSFETs; Degradation; Gate leakage; Lamps; Large scale integration; Leakage current; MOSFET circuits; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-00-1

Type

conf

DOI

10.1109/.2005.1469245

Filename

1469245