Title :
Control of process-induced damages in self-assembled porous silica/Cu damascene interconnects for 45nm node and beyond
Author :
Yagi, R. ; Chikaki, S. ; Shimoyama, M. ; Yoshino, T. ; Ono, T. ; Ishikawa, A. ; Fujii, N. ; Hata, N. ; Nakayama, T. ; Kohmura, K. ; Tanaka, H. ; Goto, T. ; Kawahara, J. ; Sonoda, Y. ; Matsuo, H. ; Seino, Y. ; Kinoshita, K. ; Kikkawa, T.
Author_Institution :
MIRAI, National Inst. of Adv. Ind. Sci. & Technol., Ibaraki, Japan
Abstract :
New methods to recover process-induced damages of a self-assembled non-periodic porous silica (k=2.1) film were developed for Cu/low-k damascene interconnects for 45nm technology node and beyond. It is shown that process-induced damages can be suppressed by employing 1,3,5,7-tetra-methylcyclotetrasiloxane (TMCTS) vapor annealing after dry etching, by using a new suppressor for a Cu plating solution, and by post Cu-CMP cleaning with ethanol. Time-dependent dielectric breakdown lifetime of the non-periodic porous silica/Cu damascene was evaluated to be more than 10 years.
Keywords :
annealing; chemical mechanical polishing; copper; electric breakdown; etching; integrated circuit interconnections; organic compounds; porous semiconductors; self-assembly; silicon compounds; 45nm node; 45nm technology node; Cu damascene interconnects; Cu-CMP cleaning; Cu/low-k damascene interconnects; SiO2-Cu; dielectric breakdown lifetime; dry etching; process-induced damages; self-assembled porous silica; tetra-methylcyclotetrasiloxane; vapor annealing; Annealing; Dielectric constant; Dry etching; Ethanol; Furnaces; Hafnium; Plasma applications; Process control; Self-assembly; Silicon compounds;
Conference_Titel :
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-00-1
DOI :
10.1109/.2005.1469247
