A novel fabrication process to downscale SiON gate dielectrics (EOT = 1.06 nm, Jgn = 8.5 A/cm2) toward sub-65nm and beyond

This paper presents a cutting-edge 65nm gate dielectrics technology featuring EOT at 1.06 nm (CET = 1.79nm), nFET Jg at 8.5 A/cm², as well as 10μm×10μm n/pMOSFET Vt of 0.078/0.148V. A novel room temperature plasma SiON is developed with a unique capability to achieve higher top-to-bottom nitrogen concentration ratio than conventional plasma SiON. In addition, nitrogen peak is moved toward top surface. Furthermore, EOT-Jg characteristics are improved by applying this novel plasma process to the post poly-etch re-oxidation step without increasing Vt. The proposed scheme demonstrates a superior interface state density with excellent resistance to boron penetration without mobility and NBTI degradation showing very promising features for gate oxynitride scaling toward 65nm and beyond high performance CMOS applications.