Title :
Nonvolatile MOSFET memory based on high density WN nanocrystal layer fabricated by novel PNL (pulsed nucleation layer) method
Author :
Lim, Seung-Hyun ; Joo, Kyong Hee ; Park, Jin-Ho ; Lee, Sang-Woo ; Sohn, Woong Hee ; Lee, Changwon ; Choi, Gil Heyun ; Yeo, In-Seok ; Chung, U-in ; Moon, Joo Tae ; Ryu, Byung-II
Author_Institution :
Center of Semicond. R&D, Samsung Electron. Co., Ltd, Gyeonggi, South Korea
Abstract :
We describe a novel technique of fabricating WN nanocrystal memory device. Pulsed nucleation layer (PNL) method is firstly introduced for the formation of uniformly distributed high density (∼ 1.6 × 1012 /cm2) nanocrystals with the size of 3 ∼ 5 nm. The WN nanocrystal memory exhibits very large threshold voltage shifts over 3.5 V and good retention and endurance characteristics. Further improvement of memory performances using stacked tunnel barrier and double layer storage node structures was also presented.
Keywords :
MOSFET; crystal growth; memory architecture; nanostructured materials; nanotechnology; nucleation; double layer storage node structures; high density WN nanocrystal layer fabrication; nonvolatile MOSFET memory; pulsed nucleation layer; stacked runnel barrier; very large threshold voltage shifts; Fabrication; Flash memory; Gas insulated transmission lines; Low voltage; MOSFET circuits; Moon; Nanocrystals; Nonvolatile memory; Research and development; Threshold voltage;
Conference_Titel :
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-00-1
DOI :
10.1109/.2005.1469263
