Author :
Doris, Bruce ; Kim, Y.H. ; Linder, B.P. ; Steen, M. ; Narayanan, V. ; Boyd, D. ; Rubino, J. ; Chang, L. ; Sleight, J. ; Topol, A. ; Sikorski, E. ; Shi, L. ; Wong, K. ; Babich, K. ; Zhang, Y. ; Kirsch, P. ; Newbury, J. ; Walker, G.F. ; Carruthers, R. ; Emi
Author_Institution :
IBM Semicond. R&D Center, Hopewell Junction, NY, USA
Abstract :
A high performance FDSOI CMOS technology featuring metal gate electrodes and high-k gate dielectrics is presented. Work-function tuning is accomplished by materials and process modification to achieve appropriate threshold voltages for FDSOI CMOS. The gate stacks exhibit an extremely thin effective inversion thickness (Tinv) down to 14A with a gate leakage current of 0.2A/cm2. This represents a six order of magnitude leakage reduction compared to Poly/SiO2. By optimizing the gate stack, the highest unstrained electron mobility is realized (207cm2A/s at Eeff=1Mv/cm) at Tinv=14A. Drive currents of 1050μA/μm and 770μA/μm at Ioff of 90nA/μm and 28nA/μm are achieved for nMOS and pMOS respectively. This is the highest reported pFET drive current for metal gate transistors with high-k gate dielectrics. We also present FDSOI metal gate high-k ring oscillators and SRAM cells with static noise margin (SNM) of 328mV at Vdd=1,2V.
Keywords :
CMOS integrated circuits; MIS structures; MOSFET; SRAM chips; dielectric materials; electron mobility; silicon-on-insulator; FDSOI metal gate high-k ring oscillators; SRAM cells; gate leakage current; high performance FDSOI CMOS technology; high-k gate dielectric; inversion thickness; metal gate electrode; metal gate transistors; nMOS; pFET drive current; pMOS; static noise margin; threshold voltage; unstrained electron mobility; work-function tuning; CMOS process; CMOS technology; Dielectric materials; Electrodes; Electron mobility; High K dielectric materials; High-K gate dielectrics; Leakage current; Threshold voltage; Tuning;
