Title :
A 65nm low power CMOS platform with 0.495μm2 SRAM for digital processing and mobile applications
Author :
Utsumi, K. ; Morifuji, E. ; Kanda, M. ; Aota, S. ; Yoshida, T. ; Honda, K. ; Matsubara, Y. ; Yamada, S. ; Matsuoka, F.
Author_Institution :
Syst. LSI Div., Toshiba Corp., Yokohama, Japan
Abstract :
In this paper, a 65nm CMOS platform featuring low power transistors and high density SRAM (CMOS5L) is reported. It offers wide range of Vth lineup and very low gate leakage as 0.06A/cm2 by optimization of halo implantation and gate oxidation process. Pulse nitridation is applied to suppress Vth variations. Obtained characteristics of MOSFET places top class among devices reported. High density SRAM for CMOS5L with the cell size of 0.495μm2 is developed. We demonstrate highly stable operation by 7Mb CMOS5L SRAM array. This SRAM has low power property less than 100μW.
Keywords :
CMOS memory circuits; MOSFET; SRAM chips; cellular arrays; circuit optimisation; digital signal processing chips; ion implantation; oxidation; 100 muW; 65 nm; 7 MByte; CMOS5L; MOSFET; digital processing; gate oxidation process optimization; halo implantation optimization; high density SRAM; low power CMOS platform; low power transistors; mobile application; CMOS process; CMOS technology; Energy consumption; Gate leakage; MOS devices; MOSFET circuits; Nitrogen; Oxidation; Power MOSFET; Random access memory;
Conference_Titel :
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-00-1
DOI :
10.1109/.2005.1469273
