Ultra-low standby power (U-LSTP) 65-nm node CMOS technology utilizing HfSiON dielectric and body-biasing scheme

This paper reports 65-nm node ultra-low standby power CMOS technology for mobile applications, utilizing the combination of HfSiON FET and back-biasing scheme for the first time. With well-optimized channel, offset-spacer and halo conditions, physical gate length is successfully scaled down to 55 nm with excellent V_th roll-off and small DIBL, for both surface channel nFET and buried channel pFET. The record I_on/I_off ratio, the drive current of 510/220 μA/μm with off-state leakage of 20/20 pA/μm, are obtained. We have also demonstrated body-biasing scheme feasibility for further subthreshold leakage (I_subth) reduction. By exploiting Fermi-level-pinning effect, we have reduced the channel doping concentration and suppressed gate induced drain leakage (I_GIDL) even under reverse body-biasing condition. Total standby leakage (I_subth+I_GIDL+I_g) are reduced to 1.4/0.32 pA/μm at V_dd= 0.8 V and Vb= ±1 V, which is the smallest value ever reported for 65nm-node LSTP.