Title :
A fully-pipelined single-precision floating point unit in the synergistic processor element of a CELL processor
Author :
Oh, Hwa-Joon ; Mueller, Silvia M. ; Jacobi, Christian ; Tran, Kevin D. ; Cottier, Scott R. ; Michael, Brad W. ; Nishikawa, Hiroo ; Totsuka, Yonetaro ; Namatame, Tatsuya ; Yano, Naoka ; Machida, Takashi ; Dhong, Sang H.
Author_Institution :
IBM Syst. & Technol. Group, Austin, TX, USA
Abstract :
The floating point unit in the synergistic processor element of a CELL processor is a fully-pipelined 4-way SIMD unit designed to accelerate media and data streaming. It supports 32-bit single-precision floating point and 16-bit integer operands with two different latencies, optimizing the performance of critical single-precision multiply-add operations. It employs fine-grained clock gating for power saving. Architecture, logic, circuits and integration are co-designed to meet the performance, power, and area goals.
Keywords :
CMOS integrated circuits; VLSI; floating point arithmetic; logic gates; microprocessor chips; pipeline arithmetic; silicon-on-insulator; 16 bit; 16-bit integer operands; 32 bit; 32-bit single-precision floating point; CELL processor; CMOS; SIMD unit; SOI; VLSI; data streaming; fine-grained clock gating; floating point unit; microprocessor; multiply-add operation; static circuits; synergistic processor element; Adders; CMOS logic circuits; Delay; Design optimization; Latches; Logic design; Multiplexing; Streaming media; Timing; Very large scale integration;
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
DOI :
10.1109/VLSIC.2005.1469325
