Title :
A 5.0Gbps/pin packet-based DRAM with low latency receiver and process insensitive PLL
Author :
Choi, Jung-Hwan ; Sohn, Young-Soo ; Kim, Chan-Kyoung ; Park, Won-Ki ; Lee, Jae-Hyung ; Kang, Uksong ; Byun, Gyung-Su ; Park, In-Soo ; Kim, Byung-Chul ; Hwang, Hong-Sun ; Kim, Chang-Hyun ; Cho, Soo-In
Author_Institution :
DRAM Design, Samsung Electron. Co., Hwasung, South Korea
Abstract :
A 2.0V, 256Mbit packet-based DRAM with bandwidth of 10GB/s (5.0Gbps × 16pin) was fabricated. To have high data bandwidth and stable clock generation, high performance input receiver and process insensitive PLL bias scheme were used. To increase the write speed of the cell array, write without 10 pre-charge scheme was employed. The power consumption and area of the chip are 2.4W and 7.2×10.2mm2 respectively.
Keywords :
DRAM chips; clocks; flip-flops; network analysis; phase locked loops; 10 Gbit/s; 10.2 mm; 2.0 V; 2.4 W; 256 Mbit; 7.2 mm; DRAM; PLL; cell array; clock generation; input receiver; write speed; Bandwidth; Circuits; Clocks; Delay; Energy consumption; Frequency; Inverters; MOS devices; Phase locked loops; Random access memory;
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
DOI :
10.1109/VLSIC.2005.1469331
