4.0GHz 0.18μm CMOS PLL based on an interpolate oscillator

Author

Gebara, Fadi H. ; Schaub, Jeremy D. ; Drake, Alan J. ; Nowka, Kevin J. ; Brown, Richard B.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA

fYear

2005

fDate

16-18 June 2005

Firstpage

100

Lastpage

103

Abstract

Phase-locked loops (PLLs) have not been the bottleneck in processor frequency performance. However, new digital circuit families, architectural improvements, and deeper pipelines have challenged this trend. In this paper, we present two novel interpolative oscillators and a phase-locked loop which is capable of clocking even the most demanding logic families. Experimental results, from a TSMC 0.18μm process, show oscillator frequencies as high as 4.6GHz and rms jitter values of less then 1.25ps. Additionally, the PLL was able to lock to form a 4GHz output signal. These results are among the best published to date in this process.

Keywords

clocks; phase locked loops; voltage-controlled oscillators; 0.18 micron; 4.0 GHz; 4.6 GHz; CMOS; clock; digital circuit family; interpolate oscillator; interpolative oscillators; oscillator frequency; phase-locked loops; processor frequency performance; rms jitter; Delay effects; Digital circuits; Frequency; Interpolation; Inverters; Jitter; Phase locked loops; Pipelines; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-01-X

Type

conf

DOI

10.1109/VLSIC.2005.1469343

Filename

1469343