A low-IF CMOS single-chip Bluetooth EDR transmitter with digital I/Q mismatch trimming circuit

Author

Miyashita, D. ; Ishikuro, H. ; Shimada, T. ; Tanzawa, T. ; Kousai, S. ; Kobayashi, H. ; Majima, H. ; Agawa, K. ; Hamada, M. ; Hatori, F.

Author_Institution

SoC R&D Center, Toshiba Corp., Kawasaki, Japan

fYear

2005

fDate

16-18 June 2005

Firstpage

298

Lastpage

301

Abstract

A single-chip low-IF transmitter for the Bluetooth enhanced data rate (max. 3Mbps) was fabricated in 0.18-μm CMOS process. A quantitative study on the relation between the VCO pulling, intermediate frequency, and the linearity of the PA shows that the 1MHz-IF is the best solution. By a digital DC offset cancellation and I/Q mismatch trimming techniques, the LO and image signal leakages are suppressed below -40dBc and -50dBc, respectively.

Keywords

Bluetooth; CMOS integrated circuits; power amplifiers; radio transmitters; radiofrequency integrated circuits; voltage-controlled oscillators; 0.18 micron; 1 MHz; Bluetooth; CMOS process; EDR transmitter; RF CMOS; VCO pulling; digital DC offset cancellation; digital I/Q mismatch trimming circuit; enhanced data rate; image signal leakage; local oscillator; power amplifier; single-chip low-IF transmitter; voltage controlled oscillator; Bluetooth; CMOS digital integrated circuits; CMOS process; Frequency conversion; Linearity; Power generation; Power system harmonics; Signal generators; Transmitters; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-01-X

Type

conf

DOI

10.1109/VLSIC.2005.1469390

Filename

1469390