Title :
A reconfigurable pipelined ADC in 0.18 μm CMOS
Author :
Anderson, M. ; Norling, K. ; Dreyfert, A. ; Yuan, J.
Author_Institution :
Dept. of Electrosci., Lund Univ., Sweden
Abstract :
A reconfigurable pipelined A/D converter has been implemented in a 0.18 μm RF-CMOS process. The ADC has eight configurations with a top performance of 10 bits resolution at 80 MSPS consuming 94mW. The reconfigurability is achieved by combining the cyclic and pipelined ADC architectures giving it a low level of complexity. In the conventional pipeline mode, the measured SFDR is 69 dBFS and the SNDR is 56.5 dBc for a 1.54 MHz single sinusoid tone input.
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; pipeline arithmetic; radiofrequency integrated circuits; reconfigurable architectures; 0.18 micron; 1.54 MHz; 94 mW; RF-CMOS process; analog-digital converter; cyclic ADC architectures; pipelined ADC architectures; reconfigurable pipelined ADC; Capacitors; Circuits; Clocks; Digital control; Frequency; Pipelines; Sampling methods; Signal generators; Switches; Voltage control;
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
DOI :
10.1109/VLSIC.2005.1469397
